1. Field of the Invention
The present invention relates to a semiconductor device including an active layer of zinc oxide with a controlled crystal lattice spacing and a manufacturing method thereof.
2. Description of the Background Art
It has been known for many years that zinc oxide has excellent characteristics as a semiconductor (an active layer). In recent years, active research and development of a semiconductor thin film layer of zinc oxide have been made in order to apply such a semiconductor thin film layer to a semiconductor device which includes a thin film transistor (hereinafter abbreviated as TFT), a light emitting device, a transparent conductive film, or the like.
An oxide TFT including a semiconductor thin film layer of zinc oxide has a greater electron mobility and better TFT performance than an amorphous silicon TFT having a semiconductor thin film layer of amorphous silicon (a-Si:H), which has been mainly used for liquid crystal displays. Another advantage of the oxide TFT is that high electron mobility can be expected because a crystalline thin film is formed even at a temperature as low as a room temperature. These advantages have been encouraging the development of the oxide TFTs.
TFTs using an oxide semiconductor thin film layer, such as a bottom gate TFT and a top gate TFT, have been reported. For example, the bottom gate structure includes, in order: a substrate, a gate electrode, a gate insulator, source/drain electrodes, an oxide semiconductor thin film layer, and a protective insulator. The top gate structure includes, for example, in order a substrate, a pair of source/drain electrodes, an oxide semiconductor thin film layer, a gate insulator, and a gate electrode.
If an oxide semiconductor thin film layer of zinc oxide is formed on an amorphous material (e.g., glass or plastic as used in a substrate of a display), it is known that physical constants (e.g., orientation and lattice constant) of the zinc oxide vary according to the conditions employed in the film formation. For example, “Microstructural evolution and preferred orientation change of radio-frequency-magnetron sputtered ZnO thin films.”, Journal of Vacuum and Science of Technology Part. A Vol. 14, p. 1943 (1996) shows that the orientation and lattice constant of a zinc oxide film vary according to the ratio between argon (Ar) and oxygen (O2) used as source gases in a sputtering process to form the zinc oxide film. However, this publication does not disclose how the physical properties (e.g., orientation and lattice constant) of zinc oxide affect the heat resistance of the zinc oxide or the performance of semiconductor devices which include a TFT or the like.
The effect of the orientation and the lattice constant of zinc oxide on the performance of a semiconductor device is described in Japanese Patent Publication No. 2005-150635. Japanese Patent Publication No. 2005-150635 discloses that a thin film transistor exhibits preferable performance when the lattice spacing d002 of lattice planes along (002) direction ranges from 2.613 Å to 2.618 Å. In Japanese Patent Publication No. 2005-150635, TFT performance of a bottom gate TFT was measured. As shown in FIG. 16, the bottom gate TFT includes a substrate 51, a gate electrode 52, a gate insulator 53, oxide semiconductor thin film layer 54 of zinc oxide, and a pair of source/drain electrodes 55. These layers are combined in this order.
Japanese Patent Publication No. 2005-150635 defines a preferable range of lattice spacing d002 of oxide semiconductor thin film layer 54 as 2.613 Å to 2.618 Å based on X-ray diffraction values, which are mean values throughout oxide semiconductor thin film layer 54. Thus, the preferable range 2.613 Å to 2.618 Å defined by Japanese Patent Publication No. 2005-150635 for the lattice spacing d002 is calculated from mean values throughout oxide semiconductor thin film layer 54.
In bottom gate TFTs, a portion of oxide semiconductor thin film layer 54 that forms an interface between gate insulator 53 and oxide semiconductor thin film layer 54, having a thickness of 10 nm or less, functions as a channel region. The channel region has a poorer crystallinity than the other part of oxide semiconductor thin film layer 54 since the channel region is formed at an early stage in formation of oxide semiconductor thin film layer 54.
This means that the channel area formed in oxide semiconductor thin film layer 54 at an early stage of the film formation does not always have a lattice spacing d002 that is in the range calculated from the mean value of entire oxide semiconductor thin film layer 54 as disclosed in Japanese Patent Publication No. 2005-150635.
In a practical use of a bottom gate TFT in a liquid crystal display or the like, a protective insulator is formed on the oxide semiconductor thin film layer using a heating process. Since zinc oxide has a poor heat resistance, the heat history during the protective insulator formation results in desorption of zinc or oxygen from the oxide semiconductor thin film layer as well as defects in the oxide semiconductor thin film layer. The defects form a shallow impurity level and reduce the resistance of the oxide semiconductor thin film layer.
In a bottom gate TFT, the defects caused by the formation of the protective insulator form defects in the surface of the oxide semiconductor thin film layer, which is at a back channel side of the bottom gate TFT. As described above, the bottom part of the oxide semiconductor thin film layer functions as a channel in the bottom gate TFT. The defects formed on the back channel side greatly affect the performance of the bottom gate TFT.
In producing the bottom gate TFT disclosed in Japanese Patent Publication No. 2005-150635, only vacuum deposition of source/drain electrodes 55 is performed after oxide semiconductor thin film layer 54 is formed. Thus, oxide semiconductor thin film layer 54 as described in Japanese Patent Publication No. 2005-150635 is not affected by the heat history caused during the formation of a protective insulator. In other words, the effects of heat on zinc oxide are not taken into account in defining the lattice constant range disclosed in Japanese Patent Publication No. 2005-150635. Therefore, it is not clear whether oxide semiconductor thin film layer 54 has a lattice spacing that is within the above-mentioned range during the actual use of the TFT in a liquid crystal display or the like after a protective insulator is formed in the TFT.